The present invention relates to a digital radio receiver or a receiver section of a radio transceiver and to integrated circuits embodying the digital radio receiver.
An article entitled xe2x80x9cQuadrature Bandpass xcex94xcexa3 Modulation for Digital Radioxe2x80x9d, IEEE Journal of Solid-State Circuits. Vol 32. No. 12, December 1997, pages 1935 to 1950, by S. A. Jantzi, K. W. Martin and Adel S. Sedra, mentions that a critical component in low-IF receiver architectures is one that performs bandpass analogue to digital conversion on quadrature signals. This article mentions a low IF variant of a direct conversion receiver having I and Q mixer outputs comprising narrow band signals at an IF. These outputs undergo complex, or quadrature, anti-alaising filtering and the outputs are then digitised in concert with a quadrature bandpass Sigma-Delta modulator. The modulator takes in a complex analogue input signal and produces a complex digital output which is representative of the complex input within a narrow bandwidth. The spectrum of the output, being complex, may be asymmetric about dc. Mathematical simulations of high order Sigma-Delta modulators do not always lead to stable implementations and in consequence are difficult to design.
FIG. 9 of this prior art article also discloses a quadrature bandpass Sigma-Delta modulator comprising several complex resonators. Each of the complex resonators is a simple complex filter which forms a complex pole on the unit circle. By having feedback around the quantizer, these poles form noise-shaping zeros responsible for nulling in-band quantization noise. FIG. 11 of this prior art article discloses a fourth order complex modulator having four complex poles inside a global feedback loop. The real and imaginary inputs are oversampled and the samples are supplied by way of respective capacitors to complex feed-ins of four complex resonators of the complex modulator. The real and imaginary channels each has a latched comparator that produces a one-bit output and drives a one-bit feedback digital to analogue converter DAC. The DAC output levels are fed back into the respective modulator stages through respective capacitors. The described structure allows independent positioning of all transfer function poles and zeros, which enables noise shaping to be performed at an arbitrary fraction of the sampling frequency and for noise-shaping zeros to be spread optimally across the band of interest. Optimal positioning of zeros within the band of interest significantly increases the signal-to-noise ratio (SNR) obtainable by a given modulator order. The described circuit has no provision for anti-alising which will occur due to the inputs to the Sigma-Delta modulator being sampled at the bit rate of the outputs from the latched comparators. By having the sampling before the loop filter, the loop filter cannot provide any anti-alising filtering which leads to interference from unwanted signals. The cited article discloses the provision of a complex anti-alias filter and amplifier to reduce this interference before the signals are applied to the Sigma-Delta modulator. This anti-alias filter has to have a high out-of-band attenuation and as a consequence it has a high power consumption and requires close matching. Such a filter if implemented as an integrated circuit migh require external (or off-chip) passive components.
United States of America Patent Specification U.S. Pat. No. 5,764,171 discloses a quadrature signal conversion device comprising frequency translation means for converting a received signal into frequency down converted quadrature related signals. Each of the quadrature related signals is supplied to a respective Sigma-Delta converter comprising a signal combining stage having inputs for one of the downconverted signals and for a signal fed back from an output of the Sigma-Delta converter. An output of the combining stage is coupled to an input of a filter stage, to which input is coupled the output of the filter stage of the other Sigma-Delta converter so that the Sigma-Delta converters are cross coupled thereby forming a polyphase filter. A quantiser is coupled to each of the filter stages to provide output signals suitable for processing in a digital signal processor (DSP) which produces the receiver""s output signal. Using a single filter stage reduces the quantisation noise but there is a desire to reduce the quantisation noise further.
An object of the present invention is to be able to make an integratable receiver or receiver section of a transceiver with improved quantisation noise reduction.
According to a first aspect of the present invention there is provided a receiver comprising an input, first and second quadrature related frequency translation stages coupled to the input, first and second continuous time, low pass Sigma-Delta modulators coupled to the first and second frequency translation stages, respectively, for producing oversampled digital signals, the first and second Sigma-Delta modulators having a low frequency bandpass response, means for demodulating the digitised outputs, and means for altering the bit rate of the oversampled signals to a rate required by the demodulating means, wherein the first and second Sigma-Delta modulators each comprise a corresponding plurality of N serially connected integrators, where N is an integer having a value of at least 2, and wherein the second to Nth integrators of the first Sigma-Delta modulator are cross-coupled with the corresponding integrator of the second Sigma-Delta modulator.
By the first and second Sigma-Delta modulators being continuous time modulators, the sampling follows the loop filter thereby providing anti-alias filtering. Since the cross-coupled first and second Sigma-Delta modulators have a low frequency bandpass response matching is easier to achieve. Good matching is of importance because it is not easy to remove the error component of the wanted and interfering signal once it has been generated and also because of the effect on the quantisation noise spectrum. Since the cross-coupled modulators have a low frequency bandpass response they can be implemented as a low power integrated circuit. By not cross-coupling all the integrators, especially the first integrator, dc offsets are reduced.
In an embodiment of the receiver, each of the Sigma-Delta converters includes a continuous time loop filter before the analogue-to-digital converter (ADC) in order to pass the wanted signal band but apply heavy attenuation to signals at frequencies higher than half the sampling rate thereby avoiding aliasing.
The first and second quadrature related frequency translation stages may be low IF or, alternatively, zero IF stages.
A pre-filter, for example a polyphase filter, may be coupled between a respective output of each of the first and second frequency translation stages and a respective one of the first and second Sigma-Delta modulators. The provision of the pre-filters provides low order anti-aliasing filtering and blocking suppression which avoids the Sigma-Delta modulators having to block signals which it is estimated could require an increase in its dynamic range and a very substantial increase line rate.
Automatic gain control means may be coupled between a respective output of each of the first and second frequency translation stages, operating as low IF stages, and the Sigma-Delta modulators. An advantage of providing gain control is that it reduces the dynamic range of the Sigma Delta modulators further.
When the first and second frequency translation stages are zero IF stages, the products of mixing are applied to low pass filters.
The bit rate altering means may comprise at least one decimating means.
In an embodiment of the present invention the oversampled outputs of the first and second Sigma-Delta modulators are applied to first decimating means coupled to outputs of the modulators for reducing the sampling rate thereby reducing the noise power, derotation means are coupled to the first decimating means, the derotation means producing a relatively pure sine wave signal thereby preventing large out-of-band quantisation noise from being aliased in band, and second decimating means are coupled to the derotation means for reducing the sampling rate further.
The first decimating means may be cross coupled in order to give bandpass noise shaping at the low IF thereby reducing the need for a higher over-sampling factor.
According to a second aspect of the present invention there is provided an integrated circuit comprising a receiver in accordance with the first aspect of the present invention.